1. Field of the Invention
The present invention relates to a pipelined A/D converter circuit, and in particular, to a pipelined A/D converter circuit provided with an A/D converter circuit parts of respective stage each including a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit.
2. Description of the Related Art
Conventionally, pipelined A/D converter circuits have been widely used as high-speed high-resolution A/D converter circuits for use in communications, images and so on. The pipelined A/D converter circuits are required to have an increased speed and low power consumption.
FIG. 17 shows a configuration of a conventional pipelined A/D converter circuit. The pipelined A/D converter circuit 910 is configured to include a sample hold circuit 11, and a plurality of A/D converter circuit parts 920-1 to 920-k. The A/D converter circuit parts 920-1 to 920-k are connected to each other in cascade. Moreover, each of the A/D converter circuit parts 920-1 to 920-k functions as a pipeline stage serving as a fundamental operation circuit. In the following description, the A/D converter circuit part 920-i (where “i” is an integer of 1 to k) is referred to as an i-th stage. The A/D converter circuit parts 920-1 to 920-k are each configured to include a sample hold part 21, an ADC 22, a DAC 23, and a residue gain amplifier 24. The sample hold part 21 samples and holds an input signal V1. The ADC 22 converts the analog input signal V1 into an n1-bit digital signal, and outputs the resulting signal. The DAC 23 converts the digital signal converted by the ADC 22 into an analog signal. The residue gain amplifier 24 amplifies a result obtained by subtracting a signal outputted from the DAC 23 from the signal sampled and held by the sample hold part 21, and outputs the resulting signal as an output signal V2. Moreover, the sample hold part 21, the ADC 22, the DAC 23 and the residue gain amplifier 24 are collectively referred to as a multiplier D/A converter circuit (Multiplying Digital to Analog Converter; MDAC).
Referring to FIGS. 18A and 18B, each pipeline stage alternately repeats sample phase operation and amplification phase operation by switchover of the connection of the circuits with a switch in a constant time cycle. That is, as shown in FIG. 18A, when the (i−1)-th stage operates in the sample phase, the i-th stage, or the rear stage operates in the amplification phase. Conversely, as shown in FIG. 18B, when the (i−1)-th stage operates in the amplification phase, the i-th stage operates in the sample phase. The sample phase is the phase in which an input voltage VIN is sampled by charging sampling capacitors C1 and C2 with the input voltage VIN. At this time, the bottom plates of the sampling capacitors C1 and C2 are connected to the input voltage VIN, and the top plates of the sampling capacitors C1 and C2 are connected to a reference potential GND and connected to the inverted input of an operational amplifier A. The amplification phase is the phase in which the voltages sampled by C1 and C2 in the sampling phase are amplified and outputted to the rear stage. More concretely, by connecting an output of the DAC 23 with the bottom plate of C1, connecting the bottom plate of C2 with an output of the operational amplifier A, and disconnecting the top plates of C1 and C2 from the reference potential GND, VOUT that ideally satisfies VOUT=−VDAC+2VIN is outputted to the rear stage. As an example of such a pipelined A/D converter circuit, there is the pipelined A/D converter circuit described in the Patent Document 1.
A prior art document related to the present invention is Patent Document 1 of Japanese patent laid-open publication No. JP 2009-141861 A.
In the pipelined A/D converter circuit described above, the i-th stage operates in the sample phase when the (i−1)-th stage is in the amplification phase as shown in FIG. 18B. Therefore, when the (i−1)-th stage is switched over to the amplification phase and the i-th stage is switched over to the sample phase, an operational amplifier A(i−1) charges the sampling capacitors C1′ and C2′ of the i-th stage up to a voltage corresponding to a predetermined operation result. At this time, the time required for charging fluctuates due to electric charges accumulated in C1′ and C2′ before the i-th stage is switched over to the sample phase. The larger the difference between the accumulated electric charges and the target electric charges after the charging, the more a settling time consumed until the charging is completed. Although a bias current flowed to the operational amplifier A needs to be increased in order to improve the sampling rate of the pipelined A/D converter circuit by performing charging in a short time, the power consumption disadvantageously increases in this case.
In this case, when the charging time is insufficient, a settling error is generated which is an error between the actual voltage value and the target voltage value at the time of ending the charging. FIG. 19 shows characteristics of the settling error in a general pipelined A/D converter circuit. In this case, Vr is a reference voltage outputted from the DAC 23. As shown in FIG. 19, the settling error Est becomes non-linear to the input voltage Vin.
The reason why the settling error becomes non-linear to the input voltage Vin is as follows. The operational amplifier A operates so as to reduce an input potential difference that is a potential difference between a positive input and a negative input in the amplification phase. In this case, the input potential difference is large at the time of starting charging, and the operational amplifier A operates in a slewing region in which the output current becomes constant not depending on the input potential difference. On the other hand, the input potential difference becomes small as the charging progresses, and the operational amplifier A operates in a transconductance region in which the output current is proportional to the input potential difference. Since the operations in the two regions are combined together as described above, the settling error becomes non-linear to the input voltage Vin.
Since a complicated circuit configuration is required for correcting the non-linear settling error as shown in FIG. 19, the settling error should be preferably linear to the input voltage Vin. As a method of linearizing the settling error, there is the method of using an operational amplifier that does not operate in the slewing region but operates only in a transconductance drive region in a manner similar to that of the Patent Document 1. However, this method has such a problem that PSRR deteriorates because of no constant current source provided for the operational amplifier A.